1. Field of the Invention
This invention relates to an improvement on a multilayer interconnection structure for a semiconductor device and more particularly to an improvement on a contact hole pattern of said semiconductor device.
2. Description of the Prior Art
In recent years, noticeable progress has been achieved in the semiconductor-manufacturing technique, particularly in the technique of forming a multilayer interconnection structure for a semiconductor device, for example, not only a 2-ply or 3-ply type, but also a 4 or more ply type. An enlarged number of interconnection layers, however, leads to the difficulties that the step configuration on the surface of the semiconductor structure is increasingly complicated, giving rise to the deterioration of wiring characteristics and reduced reliability of wiring caused by, for example, breakage. It has hitherto been generally accepted and regarded as advantageous to enlarged as much as possible the contact hole used for connection between the desired interconnection layers. However, the enlargement of the contact hole is accompanied with the undermentioned drawbacks.
FIG. 1 is a plan view of the conventional multilayer interconnection structure. FIG. 2 is a sectional view along line A--A of FIG. 1. As seen from FIG. 2, a first interconnection layer 2 consisting of an impurity region is formed in the surface portion of a semiconductor substrate 1. A first insulating layer 3 is deposited on said surface. A contact hole 4 is bored in the that part of the first insulating layer 3 which contacts the surface of the first interconnection layer 2. A second interconnection layer 5 prepared from aluminium is formed on the surface of the first insulating layer 3. This second interconnection layer 5 is connected to the first interconnection layer 2 by means of the contact hole 4. To ensure connection between the first and second interconnection layers 2, 5, the contact hole 4 is relatively enlarged in that region where the first and second interconnection layers 2, 5 are superposed on each other, and extended along the second interconnection layer 5. A second insulating layer 6 is mounted on the first insulating layer 3 and second interconnection layer 5. A third interconnection layer 7 is laid on the second insulating layer 6. This third interconnection layer 7 intersects the second interconnection layer 5 and passes over the contact hole 4.
The conventional multilayer interconnection structure constructed as described above has the drawbacks that as seen from FIG. 2, a stepped portion of the second insulating layer 6 which is defined by the surface shape of the first insulating layer 3 above the contact hole 4 causes the third interconnection layer 7 to cover the second insulating layer 6 with less reliability. In other words, the third interconnection layer 7 is much thinner in the above-mentioned stepped portion of the second insulating layer 6. Consequently, the conventional multilayer interconnection structure has the dravbacks that the third interconnection layer 7 tends to disconnect in the aforesaid stepped portion of the second insulating layer 6; wiring characteristics are deteriorated by, for example, increased wiring resistance; and electro-migration arises particularly in the thinned portion of the third interconnection layer 7, resulting in a decline in the reliability of a multilayer interconnection structure for a semiconductor device.